M48T08 DATASHEET PDF

Logic Diagram. Signal Names. DIP Connections. SOIC Connections. Block Diagram. Absolute Maximum Ratings.

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Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table Signal names. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure Logic diagram. The monolithic chip is available in two special packages to provide a highly integrated battery-backed memory and real-time clock solution. Figure 1. The clock locations contain the year, month, date, day, hour, minute, and second in hour BCD format.

Corrections for 28, 29 leap year - valid until , 30, and 31 day months are made automatically. Byte 1FF8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting.

The eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of BiPORT? The information can be accessed by the user in the same manner as any other location in the static memory array. The control circuitry constantly monitors the single 5 V supply for an out-of-tolerance condition.

As VCC falls below the battery backup switchover voltage VSO , the control circuitry connects the battery which maintains data and clock operation until valid power returns. See Table 11 on page 22 for details. The device architecture allows ripplethrough access of data from eight of 65, locations in the static storage array. Thus, the unique address specified by the 13 address inputs defines which one of the 8, bytes of data is to be accessed.

If the address inputs are changed while E1, E2 and G remain active, output data will remain valid for output data hold time tAXQX but will go indeterminate until the next address access. The addresses must be held valid throughout the cycle.

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